In the field of integrated circuits, miniaturization has been a goal for circuit designers in order to increase processing speed and reduce energy consumption. As components continue to be reduced in size, the efficient utilization of the available silicon space on the semiconductor dies is an important consideration that cannot be avoided.
Another consideration in circuit design is the reliability of the interconnections between the integrated circuit die and the package that houses the die. Two interconnection techniques, in particular, stand out as the preferred techniques for such connections. A first technique is “wire-bonding” in which relatively long wires are used to electrically couple pads near an outer edge of a top surface of the die to pads on a top surface of a substrate of the package. A second technique is a “flip-chip” technique, which uses an array of short conductive leads, e.g. solder bumps, connecting the die directly to the substrate. The term “flip-chip” refers to the way in which the die is attached to the package. The die is flipped, with respect to the wire-bonding technique, such that the top of the die is attached to the substrate and the backside of the die faces away from the substrate.
Flip-chip packages offer some significant advantages over wire-bond packages. For instance, power can be supplied at the center of the die through solder bumps instead of just at the edges. This reduces the voltage drop at the center of the die without having to use long metal conductors to route the power to the center of the die. Other benefits of flip-chip packages are their relatively shorter interconnections, high frequency response, low inductance, and better signal-to-noise ratio.
Preferably, solder is the material of choice for establishing interconnections between the flip-chip die and the substrate. Solder provides desirable conduction and processing characteristics and reliable physical strength. To mount the die on the substrate using a conventional method, solder bumps are deposited on solder wettable conductive pads on the die and an identical pattern of solder wettable pads are deposited on the substrate. Then the solder bumps on the die are aligned with the solder pads on the substrate, and the die is placed on top of the substrate, typically with an “underfill” therebetween. Then the solder is reflowed (melted) to create a good electrical and mechanical connection.
The solder that is typically used for these solder bumps consists of about 95% to about 97% lead (Pb) and about 3% to about 5% tin (Sn). Most lead (Pb) used in solder contains a Pb210 isotope that naturally emits alpha particles with an energy of about 5.5 million electron volts (5.5 MeV). Solder bumps may also contain other alpha particle emitters, including, but not limited to, one or more of U235, U238, and Th232 isotopes. In addition, other elements of the flip-chip package, such as the underfill, may also emit alpha particles. However, the majority of alpha particle emission is attributable to the solder bumps.
Alpha particles are randomly emitted from the solder bumps, or other sources, and can create electron-hole pairs in the silicon. An electron-hole pair is created when an electron is displaced from its atom and a positively charged “hole” is left in its place. Each electron-hole pair in silicon requires about 3.3 electron volts (3.3 eV) for its creation. An alpha particle having an initial energy, for example, of 5.5 MeV can create thousands of electron-hole pairs, but loses energy during electron-hole creation. If the accumulation of positive or negative charges from the electron-hole pairs reaches a certain value, the accumulated charge can change the state of a radiation-sensitive memory cell from a 0 to a 1 or vice versa. For example, these radiation-sensitive memory cells may include bit storage devices, such as storage nodes, registers, latches, etc. The bit errors in these memory cells are sometimes referred to as “soft errors”, since the semiconductor component eventually returns to its original configuration and is not permanently affected. Nevertheless, soft errors degrade the integrity of the memory cells and are unacceptable. Therefore, the location of the solder bumps with respect to radiation-sensitive components is a design consideration that should normally be taken into account.
In order to reduce soft errors in the memory cells, a few solutions have been proposed in the prior art. One solution involves placing a “blocking” region in a layer adjacent to the solder bumps of the flip-chip die for blocking alpha particle radiation. The blockage region typically extends beyond the area directly under the solder bump, such that it will be large enough to block alpha particles emitted from a solder bump to such a degree that the energy of any alpha particles will predictably have the same or less chance of causing an error than the underfill. One problem with this solution, however, is that the blocking region prevents any type of semiconductor component from being placed in these locations, thereby reducing the area on the silicon that can be used for component placement. Also, placement engines in the prior art are designed to simply restrict the placement of any component at these blocked regions. This results in unusable, wasted space on the silicon.
Another prior art method for reducing soft errors is by designing the memory cells as “alpha-hardened” cells. Alpha-hardened cells contain circuitry that is better able to withstand alpha particle strikes. In this respect, a much greater energy from the alpha particles will be required to change the state of these alpha-hardened components. However, one problem with this solution is that the alpha-hardened memory elements are typically three to four times larger than normal memory elements. Also, since a circuit designer will usually not know beforehand which memory elements might be placed under the solder bumps, the designer will usually convert all memory elements to alpha-hardened elements to be safe. Since these components are larger, they will naturally take up more space on the silicon, thereby leaving less space on the silicon for additional components.
Another prior art solution to the soft error problem is the use of “low-alpha emitting solder”. This type of solder can be made by removing all alpha particle emitting isotopes, such as Pb210, from the lead. However, completely separating the radioactive isotopes from the lead in the solder bumps is both difficult and expensive. Another solution involves providing an alpha particle absorbing material. However, this too is an expensive solution.
Therefore, there is a need in the art for a better solution for reducing soft errors in memory cells, particularly a solution that overcomes the deficiencies of the prior art. Systems and methods are needed for better utilizing the space on the silicon die while reducing the number of soft errors in the memory elements and keeping material costs low. In this way, the reliability of the semiconductor device can be enhanced without extra costs. What is also needed is a semiconductor die having relatively short distances between local clock buffers and storage cells or components to permit fast clock rates therebetween.
Various patents containing subject matter relating directly or indirectly to the field of the present invention include, but are not limited to, the following:
U.S. Pat. No. 4,887,236 to Schloemann for “Non-volatile, radiation-hard, random-access memory,” Dec. 12, 1989.
U.S. Pat. No. 5,594,262 to Lee et al. for “Elevated temperature gallium arsenide field effect transistor with aluminum arsenide to aluminum gallium arsenide mole fractioned buffer layer,” Jan. 14, 1997.
U.S. Pat. No. 5,886,375 to Sun for “SRAM having improved soft-error immunity,” Mar. 23, 1999.
U.S. Pat. No. 5,999,440 to Crafts for “Embedded DRAM with noise-protecting substrate isolation well,” Dec. 7, 1999.
U.S. Pat. No. 6,043,429 to Blish, II et al. for “Method of making flip chip packages,” Mar. 28, 2000.
U.S. Pat. No. 6,329,712 to Akram et al. for “High density flip chip memory arrays,” Dec. 11, 2001.
U.S. Pat. No. 6,436,737 to Malladi for “Method for reducing soft error rates in semiconductor devices,” Aug. 20, 2002.
U.S. Pat. No. 6,483,134 to Weatherford et al. for “Integrated circuits with immunity to single event effects,” Nov. 19, 2002.
U.S. Pat. No. 6,504,256 to Shah et al. for “In-situ radiation protection of integrated circuits,” Jan. 7, 2003.
U.S. Pat. No. 6,507,511 to Barth, Jr. et al. for “Secure and dense SRAM cells in EDRAM technology,” Jan. 14, 2003.
U.S. Pat. No. 6,531,759 to Wachnik et al. for “Alpha particle shield for integrated circuit,” Mar. 11, 2003.
U.S. Pat. No. 6,538,334 to Akram et al. for “High density flip chip memory arrays,” Mar. 25, 2003.
U.S. Pat. No. 6,548,392 to Akram et al. for “Methods of a high density flip chip memory arrays,” Apr. 15, 2003.
U.S. Pat. No. 6,693,820 to Nii et al. for “Soft error resistant semiconductor memory device,” Feb. 17, 2004.
U.S. Pat. No. 6,724,676 to Schneider et al. for “Soft error improvement for latches,” Apr. 20, 2004.
U.S. Pat. No. 6,891,743 to Ohbayashi et al. for “Semiconductor memory device having a capacitive plate to reduce soft errors,” May 10, 2005.
U.S. Pat. No. 7,081,635 to Baumann for “High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments,” Jul. 25, 2006.
U.S. Patent Application Publication No. 20040063288 to Kenney et al. for “System and method for reducing soft error rate utilizing customized epitaxial layers,” Apr. 1, 2004.
The dates of the foregoing publications may correspond to any one of priority dates, filing dates, publication dates and issue dates. Listing of the above patents and patent applications in this background section is not, and shall not be construed as, an admission by the applicants or their counsel that one or more publications from the above list constitutes prior art in respect of the applicant's various inventions. All printed publications and patents referenced herein are hereby incorporated by referenced herein, each in its respective entirety.
Upon having read and understood the Summary, Detailed Descriptions and Claims set forth below, those skilled in the art will appreciate that at least some of the systems, devices, components and methods disclosed in the printed publications listed herein may be modified advantageously in accordance with the teachings of the various embodiments of the present invention.